Methods for device fabrication using pitch reduction and related devices

ABSTRACT

Embodiments of a method for device fabrication by reverse pitch reduction flow include forming a first pattern of features above a substrate and forming a second pattern of pitch-multiplied spacers subsequent to forming the first pattern of features. In embodiments of the invention the first pattern of features may be formed by photolithography and the second pattern of pitch-multiplied spacers may be formed by pitch multiplication. Other methods for device fabrication are provided.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. patent application Ser. No.11/830,449, filed Jul. 30, 2007, pending, the disclosure of which ishereby incorporated herein in its entirety by this reference.

TECHNICAL FIELD

Embodiments of the invention relate generally to integrated circuitdevice fabrication and, more particularly, to patterning techniquesutilizing pitch reduction to fabricate a portion of the device, andassociated structures.

BACKGROUND

As a consequence of many factors, including demand for increasedportability, computing power, memory capacity and energy efficiency,electronic devices such as integrated devices, are continuously beingreduced in size. The sizes of the constituent features that form thedevices, e.g., electrical elements and interconnect lines, are alsoconstantly being decreased to facilitate this size reduction.

The trend of decreasing feature size is evident, for example, in memorydevices or devices such as dynamic random access memories (DRAM), Flashmemory, static random access memories (SRAM), ferroelectric (FE)memories, etc. To take one example, DRAM may comprise thousands tobillions of identical device components in the form of memory cells. Bydecreasing the sizes of the electrical device structures that comprise amemory cell and the widths and lengths of the conducting lines to accessthe memory cells, the memory devices can be made smaller. Additionally,storage capacities can be increased by fitting more memory cells on agiven area in the memory devices.

The continual reduction in feature sizes places ever greater demands onthe techniques used to form the features. For example, photolithographyis commonly used to pattern features, such as conductive lines and pads.The concept of pitch can be used to describe the sizes of thesefeatures. Pitch may be defined as the distance between identical pointsin two neighboring features. These features are typically defined byspaces between adjacent features, which spaces are typically filled by amaterial, such as an insulator. As a result, pitch can be viewed as thesum of the width of a feature and of the width of the space on one sideof the feature separating that feature from a neighboring feature.However, due to factors such as limitations of optics and usable lightor other radiation wavelengths, photolithography techniques each have aminimum achievable pitch, below which a particular photolithographictechnique cannot reliably form features. Thus, the minimum pitch of aphotolithographic technique is an obstacle to continued feature sizereduction.

“Pitch doubling” or “pitch multiplication” is one method for extendingthe capabilities of photolithographic techniques beyond their minimumpitch. One pitch multiplication method is illustrated in FIGS. 1A-1Fhereof and described in U.S. Pat. No. 5,328,810, issued to Lowrey etal., the entire disclosure of which is incorporated herein by reference.With reference to FIG. 1A, a pattern of lines 10 isphotolithographically formed in a photo definable layer, such as aphotoresist, which overlies a layer 20 of an expendable material, whichin turn overlies a substrate 30. As shown in FIG. 1B, the pattern isthen transferred using an anisotropic etch to the layer 20 to formplaceholders, or mandrels, 40. The photoresist lines 10 can be strippedand the mandrels 40 can be isotropically etched to increase the distancebetween neighboring mandrels 40, as shown in FIG. 1C. A layer 50 ofspacer material is subsequently deposited over the mandrels 40, as shownin FIG. 1D. Spacers 60, i.e., the material extending or originallyformed extending from sidewalls of another material, are then formed onthe sides of the mandrels 40. The spacer formation is accomplished bypreferentially etching the spacer material from the horizontal surfaces70 and 80 in a directional spacer etch, as shown in FIG. 1E. Theremaining mandrels 40 are then removed, leaving behind only the spacers60, which together act as a mask for patterning, as shown in FIG. 1F.Thus, where a given pitch previously included a pattern defining onefeature and one space, the same width now includes two features and twospaces, with the spaces defined by, e.g., the spacers 60. As a result,the smallest feature size possible with a photolithographic technique iseffectively decreased.

While the pitch is actually halved in the example above, this reductionin pitch is conventionally referred to as pitch “doubling,” or, moregenerally, pitch “multiplication.” Thus, conventionally,“multiplication” of pitch by a certain factor actually involves reducingthe pitch by that factor. The conventional terminology is retainedherein.

Because the layer 50 of spacer material typically has a single thickness90 (see FIGS. 1D and 1E) and because the sizes of the features formed bythe spacers 60 usually correspond to that thickness 90, pitch doublingtypically produces features of only one width. Devices, however,generally employ features of different sizes. For example, random accessmemory devices typically contain arrays of memory cells located in one,more central region of the active surface of the devices and logicdevices located in the outer, so-called “peripheral” regions. In thearrays, the memory cells are connected by conductive lines and, in theperiphery, the conductive lines contact landing pads for connectingarrays to logic. Peripheral features such as landing pads, however, maybe larger than the conductive lines. In addition, periphery electricaldevices, including peripheral transistors, may be larger than theelectrical devices in the array. Moreover, even if peripheral featurescan be formed with the same pitch as features in the array, because maskpatterns formed by pitch multiplication may be limited to those that areformed along the sidewalls of patterned photoresist, pitchmultiplication by itself typically does not offer the flexibility, e.g.,geometric flexibility, required to define some features, particularlywhen features vary in size above and below the pitch resolution of thephotolithographic technique used.

To overcome such limitations, some proposed methods for forming patternsat the periphery and in the array involve separately etching patternsinto the array region and then peripheral region of a substrate. Apattern in the array region is first formed and transferred to thesubstrate or intermediate hard mask layer using one mask and thenanother pattern in the periphery region is formed and separatelytransferred to the substrate using another mask. Because such methodsrequire forming the pattern in the array region first before forming theother pattern in the periphery region in order to thereafter transferthe patterns to the same level to be subsequently transferred to asubstrate, such methods are limited in their ability to form equivalentor higher quality patterns suitable for forming the conductive lines ofthe array without additional masking and etching steps required forforming the pattern for the periphery features if the array pattern isto be adequately protected. One limitation affecting the quality of thearray pattern is defects. Defects may be caused, for example, by thephotoresist material deposited between spacers so that features of alarger size may be formed in the periphery. Undesirably, the processconventionally used to form smaller, dimensionally critical, spacers inthe pattern of the array while the other larger features in the patternof the periphery are formed adds expense to the process flow withoutreducing defect potential in the array.

In addition to problems encountered in forming differently sizedfeatures on an integrated circuit device, it has been found thatconventional pitch-doubling techniques may experience difficultytransferring a pattern of spacers to a substrate. In conventionalmethods of transferring the pattern, both the spacers and the underlyingsubstrate layer or layers are exposed to an etchant. The etchants,however, may also etch the material of the spacers, albeit at a slowerrate. Thus, over the course of subsequently forming another pattern offeatures in a peripheral region of the same substrate and thentransferring the patterns to an underlying material, the etchant used toform the pattern of features in the peripheral region may remove anunacceptable amount of the material of the spacers before the patterntransfer is completed in both central and peripheral regions.

Also, a layer of material overlaid on the spacers while the features inthe peripheral region are formed may leave residual material betweenadjacent spacers which may potentially cause defects or shorts thereinwhich are subsequently transferred to one or more underlying layers.These difficulties are exacerbated by the trend towards decreasingfeature size, which, for example, leads to the need to form trencheswhich have increasingly higher depth to width, or “aspect” ratios,increasing the potential for defects when subjected to additional stepsin the process flow in order to obtain features of various sizes. Thus,in conjunction with difficulties in producing structures havingdifferent feature sizes, pattern transfer limitations make theapplication of pitch multiplication principles to integrated circuitdevice manufacture even more difficult.

Accordingly, it would be desirable to provide enhanced methods offorming features of different sizes on semiconductor device structures,especially where some features are formed below the minimum sizeachievable using photolithographic and other conventional lithographytechniques, and in conjunction with pitch multiplication.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1F show cross-sectional side views of a sequence of maskingpatterns for forming conductive lines in accordance with a conventionalpitch doubling method.

FIG. 2 shows a schematic top view of a partially formed semiconductordevice, in accordance with embodiments of the invention.

FIG. 3 shows a cross-sectional side view of a portion of the partiallyformed semiconductor device of FIG. 2, in accordance with embodiments ofthe invention.

FIG. 4 shows a cross-sectional side view of the portion of partiallyformed semiconductor device of FIG. 2 after forming a pattern offeatures in a selectively definable layer in the periphery of the devicein accordance with embodiments of the invention.

FIG. 5 shows a cross-sectional side view of the portion of partiallyformed semiconductor device of FIG. 2 after transferring the pattern offeatures into a first hard mask layer in accordance with embodiments ofthe invention.

FIG. 6 shows a cross-sectional side view of the portion of partiallyformed semiconductor device of FIG. 2 after stripping off the materialof the selectively definable layer in accordance with embodiments of theinvention.

FIG. 7 shows a cross-sectional side view of the portion of partiallyformed semiconductor device of FIG. 2 after layering on anotherselectively definable layer over the pattern of features and upon asecond hard mask layer in accordance with embodiments of the invention.

FIG. 8 shows a cross-sectional side view of the portion of partiallyformed semiconductor device of FIG. 2 after forming a pattern of linesin the another selectively definable layer in the array of the device inaccordance with embodiments of the invention.

FIG. 9 shows a cross-sectional side view of the portion of partiallyformed semiconductor device of FIG. 2 after widening spaces betweenlines in the another selectively definable layer in accordance withembodiments of the invention.

FIG. 10 shows a cross-sectional side view of the portion of partiallyformed semiconductor device of FIG. 2 after depositing a layer of spacermaterial over the patterns in accordance with embodiments of theinvention.

FIG. 11 shows a cross-sectional side view of the portion of partiallyformed semiconductor device of FIG. 2 after etching the layer of spacermaterial in accordance with embodiments of the invention.

FIG. 12 shows a cross-sectional side view of the portion of partiallyformed semiconductor device of FIG. 2 after etching the layer of spacermaterial and stripping the lines of the another selectively definablelayer in accordance with embodiments of the invention.

FIG. 13 shows a cross-sectional side view of the portion of partiallyformed semiconductor device of FIG. 2 after depositing a protectivelayer of material over the patterns in accordance with embodiments ofthe invention.

FIG. 14 shows a top view of the portion of partially formedsemiconductor device of FIG. 2 after forming a protective mask in theprotective layer of material over the patterns in accordance withembodiments of the invention.

FIG. 15A shows a top view of the portion of partially formedsemiconductor device of FIG. 2 after forming a “loop chop” etch of apattern exposed by the protective mask in accordance with embodiments ofthe invention.

FIG. 15B shows a cross-sectional side view of the portion of partiallyformed semiconductor device of FIG. 2 after stripping the material ofthe protective mask and the lines from the device providing a modifiedpattern in accordance with embodiments of the invention.

FIG. 16 shows a cross-sectional side view of the portion of partiallyformed semiconductor device of FIG. 2 after transferring the modifiedpattern to a primary hard mask layer ready for transferring into thesubstrate of the partially formed device.

DETAILED DESCRIPTION

According to an embodiment of the invention, a method for semiconductordevice fabrication by what may be termed “reverse pitch reduction flow”includes patterning a first pattern of features above a substrate andpatterning a second pattern of pitch-multiplied spacers subsequent topatterning the first pattern of features. In embodiments of theinvention, the first pattern of features may be formed usingconventional lithography and the second pattern of pitch-multipliedspacers may be formed by a pitch multiplication technique. Embodimentsof the invention also encompass structures associated with the methodsdisclosed.

Embodiments of the invention may have particular utility in fabricationof NAND Flash devices, wherein the first pattern of features maycomprise gates in a peripheral region of the device and the secondpattern of features may comprise word lines in a central region thereof.Embodiments of the invention may also be employed in fabrication of DRAMmemory, phase change memory and programmable gate array (PGA) devices.

Reference will now be made to the Figures, wherein like numerals referto like features and elements throughout. It will be appreciated thatthese Figures are not necessarily drawn to scale.

In embodiments of the invention, a sequence of material layers is formedthat allows formation of a mask for processing a substrate.

FIG. 2 shows a top view of a portion of a partially formed integratedcircuit device 100. While the embodiments of the invention may be usedto form any device, they are particularly advantageously applied to formdevices having arrays of electrical devices, including memory cellarrays for volatile and non-volatile memory devices such as DRAM, ROM,phase change, or Flash memory, including NAND Flash memory, orintegrated devices having logic or gate arrays. For example, the logicarray may be a field programmable gate array (FPGA) having a core arraysimilar to a memory array and a periphery with supporting logics. Also,the array may be a fine pitch repetitive logic circuitry or embeddedmemory on a processor, as additional examples. Consequently, theintegrated circuit device 100 may be, e.g., a memory chip or aprocessor, which may include both a logic array and embedded memory, orany other integrated device having a logic or a gate array.

The integrated circuit device 100 includes a central region 102, whichmay be termed the “array,” at least partially bounded by a peripheralregion 104, which may be termed the “periphery.” It will be appreciatedthat, in a completed integrated circuit device, the array 102 willtypically be densely populated with conducting lines and electricaldevices such as transistors and capacitors. In a memory device, theelectrical devices form a plurality of memory cells, which areconventionally arranged in a regular grid pattern at the intersectionsof word lines and bit lines. Desirably, pitch multiplication may be usedto form features in the array 102, as discussed below. On the otherhand, the periphery 104 typically comprises features larger than thosein the array 102. Conventional photolithography, rather than pitchmultiplication techniques, is generally used to pattern features, suchas logic circuitry, in the periphery 104, because the geometriccomplexity of logic circuits located in the periphery 104 makes usingpitch multiplication difficult, whereas the regular grid typical ofelement patterns in the array 102 is conducive to pitch multiplication.In addition, some devices in the periphery require larger geometries dueto electrical constraints, making pitch multiplication less advantageousthan conventional photolithography for such devices. In addition topossible differences in relative scale, it will be appreciated by one ofordinary skill in the art that the relative positions, and the number,of periphery 104 and array 102 regions in the integrated circuit device100 may vary from that depicted.

FIG. 3 shows a cross-sectional side view of the partially formedintegrated circuit device 100. Various layers 120-150 are provided formasking above a substrate 110 comprising a layer of semiconductormaterial. In one NAND Flash embodiment, the substrate 110 may comprise aconventional polysilicon/WSi_(x)/oxide gate stack or metal gate stackarray. The layers 120-150 will be etched to form a mask for patterningthe substrate 110, as discussed below.

The materials for the layers 120-150 overlying the substrate 110 areselectively chosen based upon consideration of the chemistry and processconditions for the pattern forming and pattern transferring stepsdiscussed herein. Because the layers 120-150 between a topmostselectively definable layer 150 and the substrate 110 function totransfer a pattern derived from the selectively definable layer 150 tothe substrate 110, the layers 120-140 between the selectively definablelayer 150 and the substrate 110 are chosen so that they may beselectively etched relative to other exposed materials. It will beappreciated that a material is considered selectively, orpreferentially, etched when the etch rate for that material uponexposure to a given etchant is substantially greater, on the order of atleast about 2-3 times greater to at least about 40 times greater thanthe etch rate for adjacent materials exposed to the same etchant.Because a function of the layers 130-150 overlying the primary hard masklayer 120 is to allow well-defined patterns to be formed in layer 120,it will be appreciated that one or more of the layers 130-150 may beomitted or substituted if suitable other materials, chemistries and/orprocess conditions are used.

In the illustrated embodiment, the selectively definable layer 150,which may comprise an optically or mechanically patternable layeroverlies a hard mask, or etch stop, layer 140, which overlies a hardmask layer 130, which overlies the mask layer 120, which overlies thesubstrate 110 to be processed (e.g., etched) through a mask.Beneficially, the mask through which the substrate 110 is processed isformed in the hard mask layer 130 and/or in the mask layer 120.

With continued reference to FIG. 3, the selectively definable layer 150is photodefinable, e.g., formed of a photoresist, including anyphotoresist known in the art. For example, the photoresist may be anyphotoresist compatible with 157 nm, 193 nm, 248 nm or 365 nm wavelengthsystems, 193 nm wavelength immersion systems, extreme ultravioletsystems (including 13.7 nm wavelength systems) or electron beamlithographic systems. In addition, maskless lithography, or masklessphotolithography, may be used to define the selectively definable layer150. Examples of photoresist materials include argon fluoride (ArF)sensitive photoresist, i.e., photoresist suitable for use with an ArFlight source, and krypton fluoride (KrF) sensitive photoresist, i.e.,photoresist suitable for use with a KrF light source. ArF photoresistsare typically used with photolithography systems utilizing relativelyshort wavelength light, e.g., 193 nm. KrF photoresists are used withlonger wavelength photolithography systems, such as 248 nm systems. Inother embodiments, the layer 120 and any subsequent resist layers may beformed of a resist that may be patterned by nano-imprint lithography,e.g., by using a mold or mechanical force to pattern the resist. Theselectively definable layer 150 will allow a first feature having afirst size to be formed in the periphery 104. It will be appreciatedthat light reflections may decrease the precision with whichphotolithography may define the edges of a pattern. Optionally, a bottomanti-reflective coating (BARC) (not shown) may similarly be used inaddition to the first hard mask layer 140 to control light reflections.

The material for the hard mask layer 130, which functions as an etchstop and exhibits anti-reflective properties, comprises an inorganicmaterial. Suitable materials for hard mask layer 130 include siliconoxide (SiO₂) or a deep ultra-violet (DUV) dielectric anti-reflectivecoating (DARC), such as a silicon-rich silicon oxynitride. In thisembodiment of the invention, the hard mask layer 130 is a dielectricanti-reflective coating (DARC). Using a DARC for the hard mask layer 130may be particularly advantageous for forming patterns having pitchesnear the resolution limits of a particular photolithographic technique.The DARC may enhance resolution by minimizing light reflections, thusincreasing the precision with which photolithography may define theedges of a pattern. By way of nonlimiting example, the DARC layer maycomprise a DUV DARC of about 200-400 Å (20-40 nm) thickness. Othersuitable materials that exhibit adequate etch stop and anti-reflectiveproperties may be used for the hard mask layer 130.

In the illustrated embodiment, the hard mask or etch stop layer 140 isformed of silicon, e.g., poly amorphous silicon, or a film of anothermaterial that exhibits good etch selectivity to oxide. Other suitablematerials for the first hard mask layer 140 may include a silicon oxide,e.g., a low silane oxide (LSO), low temperature nitride, and a thinlayer of aluminum oxide, such as Al₂O₃. The LSO is formed by chemicalvapor deposition using a relatively low silane flow and a relativelyhigh N₂O precursor flow. Advantageously, such a deposition can beperformed at relatively low temperatures, e.g., less than about 550° C.,for example, less than about 400° C., to prevent damage to theunderlying primary mask layer 120, when the layer 120 is formed of atemperature-sensitive material. It will be appreciated that oxides maytypically be etched with greater selectivity relative to silicon thannitrides. For example, conventional etch chemistries for oxides mayremove the oxides at a rate more than 10 times faster than amorphoussilicon, while conventional etch chemistries for nitrides typically onlyremove the nitrides at a rate of about three times faster than polyamorphous silicon. As a result, both the spacers (discussed below) andthe second hard mask layer are preferably formed of the same material,in the form of an oxide, when the first hard mask layer is formed ofpoly amorphous silicon.

The mask layer 120 may be formed of amorphous carbon due to theexcellent etch selectivity of this material relative to many othermaterials, including a very high etch selectivity relative to the hardmask materials. Further, the transparent carbon is a form of amorphouscarbon that is highly transparent to light and that offers furtherimprovements for photo alignment by being transparent to the wavelengthsof light used for such alignment. Deposition techniques for forming suchtransparent carbon are known to those of ordinary skill in the art and,so, need not be further described. The amorphous carbon is particularlyadvantageous for transferring patterns to difficult-to-etch substrates,such as the substrate 110 comprising multiple materials or multiplelayers of materials, or for forming small and high aspect ratio featurestherein.

The combination of materials for the hard mask layers 130 and 140 areselectably chosen based upon the material used to form a first featurein the periphery 104 in combination with providing the material used toform the spacers in the array 102 allowing transfer of the pattern ormask formed by the layers, as discussed below, into the underlying masklayer 120. As previously mentioned, the mask layer 120 of the currentembodiment is formed of amorphous carbon and layer 150 is formed ofphotoresist. Optionally, other combinations of materials may be utilizedto advantage, for example and without limitation, including (spacermaterial/first hard mask material/second hard mask material):oxide/amorphous silicon/oxide; nitride/amorphous silicon/oxide;nitride/oxide/amorphous silicon; amorphous silicon/oxide/amorphoussilicon; carbon/amorphous silicon/oxide; and carbon/oxide/amorphoussilicon. It will be appreciated that the oxide may be a form of siliconoxide and the nitride may be silicon nitride. Where the spacer materialis oxide, as discussed below, the associated hard mask layer 120 is amaterial that is preferentially etchable relative to the oxide. Forexample, the hard mask layer 120 may be formed of a silicon-containingmaterial. Depending on the selection of appropriate etch chemistries andneighboring materials; examples of other materials include amorphouscarbon and etchable high dielectric materials.

In addition to selecting appropriate materials for the various layers,the thicknesses of the layers 120-150 are selectively chosen dependingupon compatibility with the etch chemistries and process conditionsdescribed herein. As discussed above, when transferring a pattern froman overlying layer to an underlying layer by selectively etching theunderlying layer, materials from both layers are removed to some degree.Thus, the upper layer is sufficiently thick so that it is not removedover the course of the pattern transfer to the underlying layer but noso thick as to create an undesirable topography.

In the illustrated embodiment, the selectively definable layer 150 isabout 2000 angstroms (“Å”) (200 nm) in thickness and, in otherembodiments, may range in thickness from 500-3000 Å (50-300 nm). It isalso recognized that the thickness of the selectively definable layer150 may be to a greater or lesser extent than the 2000 Å illustrated. Itwill be appreciated that, in cases where the layer 150 is a photoresist,the thickness of the layer 150 may vary depending upon the wavelength oflight used to pattern the layer 120. A thickness of about 500-3000 Å(50-300 nm) thick and, more specifically, a thickness of about 2000-2500Å (200-250 nm), is particularly advantageous for 248 nm wavelengthsystems.

The hard mask layer 140 has a thickness of about 150-200 Å (20 nm) and,in other embodiments, may range in thickness to a greater or lesserextent than the 200 Å illustrated. One particularly suitable thicknessis 100 Å. The hard mask layer 140 may have a thickness ranging fromabout 100 Å (10 nm) to about 400 Å (40 nm). The hard mask layer 130 isabout 200-600 Å (20-60 nm) thick and, in other embodiments, may range inthickness to a greater or lesser extent. For example, the layer 130 mayhave a thickness of about 300-500 Å (30-50 nm).

As discussed above, the thickness of the mask layer 120 is chosen basedupon the selectivity of the etch chemistry for etching the substrate andbased upon the materials and complexity of the substrate.Advantageously, a thickness for mask layer 120 of about 3000 Å (300 nm)and, in other embodiments a thickness between 1000-5000 Å (100-500 nm)is particularly effective for transferring patterns to a variety ofsubstrates, including substrates having a plurality of differentmaterials to be etched during the transfer.

Transferring patterns into a variety of substrates is accommodatedreadily when utilizing a mask layer 120 of sufficient thickness. Forexample, the illustrated substrate 110 comprising a plurality of layers(not shown) may be etched to form word lines over an array of gatestacks. The layers of the substrate 110 may include a tungsten silicidelayer overlying a polysilicon layer, which overlies anoxide-nitride-oxide (ONO) composite layer, which overlies a polysiliconlayer, the layers in combination and as previously processed comprisingan array of gate stacks.

The various layers discussed herein may be formed by variousconventional methods. For example, spin-on-coating processes may be usedto form photoresist, selectively definable layers. Various vapordeposition processes, such as chemical vapor deposition, may be used toform hard mask layers. Depositing each layer of materials may includedepositing a material by coating, layering, or spinning, for example.

A low temperature chemical vapor deposition (CVD) process may be used todeposit the hard mask layers or any other materials, e.g., spacermaterial described herein, over the mask layer 120, especially in caseswhere the mask layer 120 is formed of amorphous carbon. Advantageously,it is known to those of ordinary skill in the art that the hard masklayers 140 and 130 may be deposited at relatively low temperatures ofless than about 550° C., lower than about 450° C., and even lower thanabout 400° C. Such low temperature deposition processes advantageouslyprevent chemical or physical disruption of a mask layer 120 made ofamorphous carbon material. Various methods for forming these layers areknown to those of ordinary skill in the art and are described in U.S.Pat. No. 7,115,525, U.S. Pat. No. 6,573,030, and U.S. Pat. Pub. No.2006/0211260, the entire disclosures of each of which documents areincorporated herein by reference.

After formation of the various layers 120-150 as described above, toimprove and enhance the quality of a pattern of spacers formed by pitchmultiplication, a first pattern of features is formed according to anembodiment of the invention. Then, a second pattern of spacers may beformed by pitch multiplication, followed by subjecting the patterns to aso-called “loop chop” process to eliminate closed loops formed in themask. The pattern of features and the pattern of spacers at this pointare consolidated for transferring into the substrate. The quality of thefinal structure formed within the substrate is improved by forming ofthe first pattern of features before forming the second pattern ofspacers during a masking process. Specifically, as the second pattern ofspacers is more sensitive to masking-related sensitivities andtransferring processes than the first pattern of features, this processflow according to embodiments of the invention enables qualityimprovement in the second pattern of spacers by first subjecting theless dimensionally sensitive structures of the first pattern to theforming process.

In accordance with an embodiment of the invention, a first pattern offeatures is formed principally in the periphery of the device. Eachfeature of the first pattern includes, particularly at minimum or largercritical dimensions that are directly formable in the photodefinablematerial of the selectively definable layer, and do not require a pitchreduction or multiplication technique as is required to obtain smallercritical dimensions of the spacers of the second pattern, as will bediscussed below.

With reference to FIG. 4, a first pattern 106 of features 105 is formedin the selectively definable layer 150. The selectively definable layer150 may be patterned by, e.g., photolithography, in which the layer 150is exposed to radiation through a reticle and then developed. Afterbeing developed, the remaining photodefinable material, photoresist inthis embodiment, comprises features 105 (only one feature shown forclarity). Each feature 105 of the first pattern 106 may form variouslanding pads, transistors and local interconnects, for example andwithout limitation, and generally may have a size larger than thesmaller critical dimensions obtained with the spacers of the secondpattern, as discussed below.

After forming the first pattern 106, the hard mask layer 140 is etchedto transfer the first pattern 106 formed in layer 150 down to the hardmask layer 140 as shown in FIG. 5. The hard mask layer 140, formed ofamorphous silicon, is anisotropically etched using, for example, an HBrand Cl₂-containing plasma, and stopping the etch at the hard mask layer130. This so called “dry” etch of the HBr and Cl₂-containing plasmaetches the amorphous silicon at a rate greater than about five times,and even as great as ten times, the rate at which the photoresistmaterial of the features 105 may be etched. It is recognized thatetching hard mask layer 140 may consume some of the DARC material of thehard mask layer 130, for example, between 20-30 A (4-5 nm), which mayleave the surface of layer 130 slightly nonuniform in topography. Theuniformity of the hard mask layer 130 is addressed below when formingthe second pattern of spacers. HBr and Cl₂ chemistry-based etchantsexhibit good selectivity to oxide. Other suitable etchants may includeC₂F₆/Cl₂/O₂, SF₆, and CF₄ for example and without limitation.

With reference to FIG. 6, the first pattern 106 is cleaned whilestripping the selectively definable layer 150. The carbon materialfanning the photoresist layer 150 and DARC hard mask layer 130 maypolymerize upon contact with etchants. For example, the HBr/Cl₂ etch ofthe hard mask layer 140 may cause parts of the layers 150 and 130 topolymerize and leave a residue around features 105 in the hard masklayer 140, causing a pattern having undesirably non-uniform features.Thus, the first pattern 106 is cleaned by stripping off organicmaterial. The strip may be accomplished using, for example, an isotropicetch with O₂ plasma or other etch processes recognized as suitable by aperson of ordinary skill in the art for preserving the features 105 inthe hard mask layer 140.

Next, a second pattern of spacers is formed by pitch multiplication overthe first pattern 106 of features 105. The second pattern comprisesspacers having smaller critical dimensions than the first pattern 106 offeatures 105 as formed. In addition, the second pattern may be formedcompletely, partially, or not overlapping the first pattern 106.

Turning to FIG. 7, to allow the second pattern to be formed, aselectively definable layer 160 is formed on, and overlies, the hardmask layer 130 and first pattern 106 of features now formed in the firsthard mask layer 140 to allow for patterning of the second pattern in thearray 102.

As with the selectively definable layer 150, the selectively definablelayer 160 may be photodefinable, e.g., formed of a photoresist,including any suitable photoresist known in the art, such as a trimmablemandrel material. In addition, in other embodiments, the selectivelydefinable layer 160 may be formed of a resist suitable for patterning bynano-imprint lithography.

Optionally, while not necessarily required, a planar surface (not shown)may be formed prior to depositing the layer 160 by depositing aplanarizing material (not shown) around the features 105 and upon thesecond hard mask layer 130 when required for improving the planarity ofstructure of the to-be-patterned array for forming spacers.Specifically, the planarizing layer may be employed where the resolutionof the spacers to be formed in the second pattern may not be adequatelydefined without first providing a planarized surface. For example, aspin-on antireflective coating may be used for planarization purposes.

With reference to FIG. 8, the selectively definable layer 160 ispatterned using, e.g., the same photolithographic technique used topattern the selectively definable layer 150. Thus, a second pattern 108is formed in the selectively definable layer 160. Where the secondpattern 108 is used to mask features in the array 102, the area in theselectively definable layer 160 in the periphery 104 is preferably open,as illustrated. As noted above, however, while illustrated laterallyadjacent the first pattern 106, the second pattern 108 may partially orcompletely overlap the first pattern 106 or be completely separated fromthe first pattern 106. Thus, the use of different reference numerals(106 and 108) for these respective patterns indicates that they wereoriginally formed in different acts.

The process flow as described below results in the second pattern 108that includes a pitch or feature size smaller than the minimum pitch orresolution of the photolithographic technique used in forming it, unlikethe first pattern 106 that includes pitch or feature size equal to orgreater than the minimum pitch or resolution of the photolithographictechnique used to form the first pattern 106. It will be appreciatedthat the second pattern 108 in the array 102 may be used to form arraysof conductive feeds, contacts and other semiconductor components whentransferred into the substrate 110, for example and without limitation.

The second pattern 108 includes spaces or trenches 162, which aredelimited by photodefinable material features, or lines, 164 formed inthe photodefinable layer 160. The trenches 162 may be formed by, forexample, photolithography with 248 nm or 193 nm wavelengths light, inwhich the layer 160 is exposed to radiation through a reticle and thendeveloped as is known by a person of ordinary skill in the art. Afterbeing developed, the remaining photodefinable material, photoresist inthe illustrated embodiment, forms mask features such as the array oflines 164 (shown in cross-section only) as illustrated.

The resulting pitch of the lines 164 is equal to the sum of the width ofa line 164 and the width of a neighboring space 162. To minimize thecritical dimensions of features formed using this pattern of lines 164and spaces 162, the pitch may be at or near the limits of thephotolithographic technique used to pattern the photodefinable layer160. For example, for photolithography utilizing 248 nm light, the pitchof the lines 164 can be about 1000 Å (100 nm). Thus, the pitch may be atthe minimum pitch of the photolithographic technique and the spacerformed in the pattern as discussed below may advantageously have a pitchbelow the minimum pitch of the photolithographic technique.

As shown in FIG. 9, the spaces 162 may be widened by etching thephotoresist material of the lines 164, to form modified spaces 162 a andlines 164 a. The photoresist lines 164 are etched using an isotropicetch to “shrink” those features. Suitable etches include etches using anoxygen-containing plasma, e.g., a SO₂/O₂/N₂/Ar plasma, a Cl₂/O₂/Heplasma or an HBr/O₂/N₂ plasma. The extent of the etch is selected sothat the widths of the lines 164 a are substantially equal to thedesired spacing between the later-formed spacers (172 in FIG. 11), aswill be appreciated from the discussion below. For example, the width ofthe lines 164 may be reduced to 800-1200 Å (80-120 nm) or even furtherreduced to about 400-700 Å (40-70 nm). Advantageously, thewidth-reducing etch allows the lines 164 a to be narrower than wouldotherwise be possible using the photolithographic technique used topattern the selectively definable layer 160. In addition, the etch maysmooth the edges by removing material of the resist lines 164 a, thusimproving the line edge roughness uniformity of those lines. While thecritical dimensions of the lines 164 a may be etched below theresolution limits of the photolithographic technique, it will beappreciated that this etch does not alter the pitch of the spaces 162 aand lines 164 a, since the distance between identical relative points inthese features remains the same.

Next, as shown in FIG. 10, a layer 170 of spacer material is preferablyblanket deposited conformally over exposed surfaces, including the hardmask layer 130 and the top and sidewalls of the patterned, modifieddefinable layer 160 a. The spacer material may be any material that canact as a mask for transferring a pattern to the underlying hard masklayer 130. The spacer material is selected for deposition with good stepcoverage, at a temperature compatible with the modified definable layer160 a, and suitability for etching relative to the modified definablelayer 160 a and the underlying hard mask layer 130. Materials for thelayer 170 may include silicon, silicon oxides and silicon nitrides. Inthe illustrated embodiment, the spacer material is a silicon oxidedeposited at a relatively low temperature, such as 75° C., whichprovides particular advantages in combination with other selectedmaterials of the masking stack.

Methods for depositing the material of the spacer layer 170 may includechemical vapor deposition, e.g., using O₃ and TEOS to form siliconoxide, and atomic layer deposition, e.g., using a silicon precursor withan oxygen or nitrogen precursor to form silicon oxides and nitrides,respectively. The thickness of the spacer layer 170 is preferentiallydetermined based upon the desired width of the spacers 172 (FIG. 11).For example, in this embodiment, the layer 170 is deposited to athickness of about 200-800 Å (20-80 nm). In other embodiments, the layer170 may be deposited to a thickness ranging between 400-600 Å (40-60nm). In still other embodiments, the layer may range between about100-300 Å (10-30 nm) or to a greater or lesser extent than illustrated.The spacer layer 170 formed over the first pattern 106 of features 105in the periphery 104 of the device 100 may see uneven steps rangingabout 250 Å (25 nm) in size, which will be stripped away when formingthe spacers 172 as shown in FIG. 11 without substantial alteration ofthe features 105 as formed.

Turning now to FIG. 11, the spacers 172 are now formed in the secondpattern 108 by exposing the silicon oxide material of the spacer layer170 to an anisotropic etch to remove spacer material from horizontalsurfaces 180 of the partially formed device 100 while stopping on thesurface of the first hard mask layer 140 and the second hard mask layer130. Such an etch, also known as “spacer etch,” may be performed using afluorocarbon plasma containing, for example and without limitation,CF₄/CHF₃, C₄F₈/CH₂F₂ or CHF₃/Ar plasma. The material of the modifieddefinable layer 160 a may be selectively retained between adjacentspacers 172 while further processing to remove portions of the spacermaterial is performed in accordance with embodiments of the invention asdescribed below. Beneficially, retaining the material used to form thelines 164 a of the modified definable layer 160 a between adjacentspacers 172 enhances the quality of a portion of the spacers 172 by notsubjecting the material to extra processing or cleaning steps that mayundesirably erode or otherwise damage or displace the spacers prior totheir ultimate pattern transfer to the underlying substrate 110.

Optionally, in other embodiments of the invention as shown in FIG. 12,the modified definable layer 160 a may be removed to leave the spacers172 in freestanding alignment. In such an instance, the modifieddefinable layer 160 a may be selectively removed using an organic stripprocess as described above. Optional etch chemistries may include anoxygen-containing plasma etch, such as etching using an O₂ plasma strip.

Thus, pitch reduction or multiplication for spacers 172 has beenaccomplished. In the illustrated embodiment, the pitch of the spacers172 is roughly half that of the photoresist lines 164 and spaces 162(FIG. 8) originally formed by photolithography. Where the photoresistlines 164 had a pitch of about 2000 Å (200 nm), spacers 172 having apitch of about 1000 Å (100 nm) or less may be formed. It will beappreciated that, because the spacers 172 are formed on opposingsidewalls of each of the features or lines 164 a, the spacers 172generally follow the outline of the pattern of features or lines 164 ain the modified photodefinable layer 160 a and, so, form a closed looparound the ends of the lines 164 a. The spacers 172 form relativelysmaller features of the second pattern 108 that may be transferred tothe underlying substrate 110 together with the relatively largerfeatures 105 forming the first pattern 106. Advantageously, the firstpattern 106 and the second pattern 108 may now be subjected to so-called“loop chop” process to eliminate undesirable closed loops or otherportions of pattern material before transferring the mask to thesubstrate 110.

Optionally, a second pattern of spacers may be formed after the firstpattern of features is formed by utilizing other methods of pitchmultiplication. Other methods of pitch multiplication may requirelayering different or select layers of material above the substrate inaddition to the layers mentioned herein. For example, a method offorming a pattern of spacers by pitch multiplication is described inparagraphs [0056]-[0092] and FIGS. 2A-10 of U.S. Pub. No. 2006/0046422to Tran et al., dated Mar. 2, 2006, the entire disclosure of which isincorporated by reference herein.

In methods according to embodiments of the invention, spacer material inthe form of loops of spacer material connecting adjacent spacers 172 isetched to remove the loops and isolate the spacers 172. This etch may beused to form two separate lines of spacers 172 initially connected attheir adjacent ends by a loop of spacer material extending around theend of a line 164 a corresponding to two separate conductive paths to beformed in the substrate 110. It will be appreciated that more than twolines may be formed, if desired, by etching the spacers 172 at more thantwo locations. Other suitable method for cutting off the ends of theloops is disclosed in U.S. Pub. No. 2006/0046422 to Tran et al., datedMar. 2, 2006, the entire disclosure of which is incorporated byreference herein.

To form the separate lines, a protective mask is formed over parts ofthe lines to be retained and the exposed, unprotected part of the loopof spacer material connecting the spacer lines are then etched. Theprotective mask is then removed to leave a plurality of physicallyseparated and electrically isolated lines comprised of spacers 172.

With reference to FIG. 13, a protective material forming a protectivelayer 181 is selectively deposited around and over the spacers 172 andthe parts of the layers 130 and 160 forming the pattern 108, and, inthis embodiment, is selectively deposited around and over the features105 forming the pattern 106. The material of the protective layer 181may be a photodefinable material such as photoresist as described aboveand is sufficiently thick to protect the underlying mask during theetch. Optionally, an anti-reflective coating (“ARC”) (not shown) may beprovided under the protective layer 181, e.g., above the patterns 106and 108, to improve photolithography results as understood by a personof ordinary skill in the art. The photoresist and the optionalanti-reflective coating may be deposited using various methods known inthe art, including spin-on-coating processes. With reference to FIG. 14,a protective mask 182 is subsequently patterned in the protective layer181, e.g., by photolithography, to protect desired portions of theunderlying patterns 106 and 108 from a subsequent etch. It is recognizedthat the pattern 106 forming the features 105 may be entirely, partiallyor not covered depending upon the relative resistance to etching duringthe etch. To separate the spacers 172 of each loop into two separatelines, portions of the loops are exposed for etching in at least twoseparate locations. To simplify processing, the exposed portions of theloops are generally the ends of the loops formed by the spacers 172, asillustrated.

In other embodiments, it will be appreciated that the protective layer181 may be formed of any material that may be selectively removed, e.g.,relative to the spacers 172, the layers 130, 140, 160 a, and 170. Inthose cases, the protective mask 182 may be formed in another material,e.g., photoresist, overlying the protective layer 181.

Advantageously, where the ends of the spacers 172 extend in a straightline, the length and simple geometry of the straight lines may minimizethe precision required for forming the protective mask 182; that is, theprotective mask need only be formed so that it leaves the ends of thespacers 172 exposed. Thus, by centering the mask a selected distancefrom the ends of the spacers 172, a misaligned mask may cause slightlymore or less of the spacers 172 to be exposed, but may still accomplishthe objective of leaving the ends adequately exposed. While the marginof error for aligning the protective mask 182 is larger than if theprotective mask 182 were required to form a geometrically complex shape,it is recognized that other shapes may be formed in the protective mask182 different from the rectangular shape of the protective mask 182 asillustrated. See, for example, U.S. Pub. No. 2006/0046422 to Tran etal., the disclosure of which is incorporated herein in its entirety byreference.

With reference to FIG. 15A, the exposed portions of the spacers 172 areetched away leaving the exposed portions of the photoresist lines 164 aand the features 105 of pattern 106. Where the spacers 172 are foamedfrom silicon oxide or nitride, suitable etch chemistries may include afluorocarbon etch or in the case of spacers 172 formed of an oxide, suchas silicon oxide, the exposed loops of the spacers 172 may beisotropically etched using a wet chemistry, for example, a bufferedoxide etch. One suitable etchant for a silicon dioxide spacer materialis an HF/H₂O wet etch at a 500:1 dilution ratio. After being etched, thespacers 172 no longer form a loop with a neighboring spacer 172 asillustrated. The spacers 172 as etched thus forms a modified pattern 109of features 105 and spacers 172 with the material of the protective mask182 removed. FIG. 15B shows a side view of the resulting structure,taken along the vertical plane as indicated in FIG. 15A with thematerial of the lines 164 a removed.

Optionally, where the protective mask 182 is sufficiently thick and thelines 164 a were not previously removed, the exposed portions of thephotoresist lines 164 a may be descummed or etched away in order tofacilitate etching the exposed portions of the spacers 172. For example,an O₂/N₂ reactive ion etch, an O₂ etch, or a CF₄ and/or CHF₃ plasma etchmay be employed. Also, the exposed surface of the partially fabricateddevice 100, i.e., the portion not protected by the protective mask 182,may be cleaned prior to the etching the exposed portions of the spacers172.

With reference to FIGS. 15A and 15B, the materials of the protectivemask 182 and of the lines 164 a are selectively removed. Where thematerial is photoresist or optional ARC, etch chemistries includeanisotropic etches, such as with an SO₂-containing plasma. In otherembodiments, the mask of the partially formed device 100 may besubjected to an ashing process to remove the material of layers 181 and160 where the material of the modified pattern 109 is compatible withthe ashing process. It will be appreciated that the spacers 172 and thefeatures 105 are not attacked during this removal act and that theprimary hard mask layer 120 is protected by the second hard mask layer130. Advantageously, by selectively removing the material of the lines164 a together with the material of the protective mask 182, the innerportions of the spacers 172 are subjected to less processing than wouldbe if the material of the lines 164 a was removed prior to the “loopchop” process, beneficially enhancing resolution and reducing variationsand defects when the pattern 109 is transferred to the underlyingsubstrate 110.

According to embodiments of the invention, the modified pattern 109comprising the spacers 172 and the features 105 of the patterns 108 and106, respectively, may be simultaneously transferred to the substrate110.

With reference to FIG. 16, the second hard mask layer 130 and primaryhard mask layer 120 are etched to transfer the modified pattern 109 downto the mask layer 120, to form a pattern of components of mixed featuresize in the mask layer 120.

Optionally, before transferring the modified pattern into the layers 120and 130, the modified pattern 109 is cleaned. As noted above, the carbonmaterial forming the layers 130 and 181 may polymerize upon contact withetchants, leaving a residue around features or spacers on the hard masklayer 130, causing a modified pattern 109 having undesirably non-uniformfeature sizes. Thus, the modified pattern 109 is cleaned by strippingoff an organic material. The cleaning may be accomplished using, e.g.,an isotropic etch with O₂ plasma and may be done simultaneously whilestripping of the protective mask 182. For example, O₂ wet clean with anH₂O, H₂O₂, NH₄OH or so-called “SCI” solution.

Turning to FIG. 16, the modified pattern 109 is transferred to the masklayer 120. The transfer is accomplished by anisotropically etching thesecond hard mask layer 130 and the primary mask layer 120, using anSO₂-containing plasma. Other suitable etch chemistries include a Cl₂/O₂,HBr/O₂/N₂ or SiCl₄/O₂N₂/HBr or SiCl₄/O₂-containing plasma. As notedabove, the SO₂-containing plasma is particularly suitable as it has beenfound to have excellent selectivity for the amorphous carbon of the masklayer 120 and the DARC of the hard mask layer 130 relative to thematerial of the spacers 172 and the features 105. Thus, a thick enoughmask may be formed in the primary mask layer 120 to later effectivelytransfer the mask pattern to the substrate 110, particularly throughmultiple materials of the substrate using selective etch chemistries andwithout wearing away the mask layer 120 before the pattern transfer iscomplete.

After the modified pattern 109 is transferred to the mask layer 120, thepattern 109 is transferred to the substrate 110 using the patterned masklayer 120 as a mask. Given the disparate materials used for the masklayer 120 and the substrate 110 (e.g., amorphous carbon and silicon orsilicon compounds, respectively), the pattern transfer can be readilyaccomplished using conventional etch chemistries appropriate for etchingthe material or materials of the substrate 110 to form the finalstructures therein. The process used to transfer the modified pattern109 from the mask layer 120 and into the substrate 110 may include anysuitable process known to a person of ordinary skill in the art.

The spacers 172 and the features 105 of the modified pattern 109 may beemployed to respectively form interconnect lines such as word lines andassociated integrated device features, such as landing pads astransferred into the substrate. Methods for forming interconnects andlanding pads are disclosed in U.S. Pub. No. 2006/0046422 to Tran et al.,dated Mar. 2, 2006, the entire disclosure of which was previouslyincorporated herein by reference. Other methods for forminginterconnects and landing pad are disclosed in U.S. Pat. No. 7,115,525to Abatchev et al., dated Oct. 3, 2006, and U.S. Pub. No. 2006/0211260to Tran et al., dated Sep. 21, 2006, the entire disclosures of which areincorporated herein by reference.

It will also be appreciated that the pitch of the pattern 108 may bemore than doubled as is shown in the drawing figures herein,particularly before the modified pattern 109 is transferred to thesubstrate. For example, the pattern 108 may be further pitch multipliedby forming spacers around the spacers 172, then removing the spacers172, then forming spacers around the spacers that were formerly aroundthe spacers 172, and so on. For example, a method for further pitchmultiplication is discussed in U.S. Pat. No. 5,328,810 to Lowrey et al.,the entire disclosure of which is incorporated herein by reference. Inaddition, while embodiments of the invention may advantageously beapplied to form a modified pattern 109 having both pitch multiplied andconventionally photolithographically defined features, the patterns 106and 108 may both be pitch multiplied or may have different degrees ofpitch multiplication.

In addition, the embodiments of the invention may be employed multipletimes throughout an integrated device fabrication process to form pitchmultiplied features and conventional features in a plurality of layersor vertical levels, which may be vertically contiguous or non-contiguousand vertically separated. In such cases, each of the individual levelsto be patterned would constitute a substrate 110 and the various layers120-181 may be formed over the individual level to be patterned. It willalso be appreciated that the particular composition and height of thevarious layers 120-181 discussed above may be varied depending upon aparticular application. In one regard, the layer 120 may be sufficientlythin in order to provide structural stability to the mask, to protectthe substrate material throughout fabrication, and to allow the mask tobe transferred into the substrate 110 without complete removal of thematerial of layer 120 before the final etch is finished. For example,the thickness of the layer 120 may be varied depending upon the identityof the substrate 110, e.g., the chemical composition of the substrate,whether the substrate comprises single or multiple layers of material,the depth of features to be formed, for example, and the available etchchemistries, without limitation. In some cases, one or more layers oflayers 120-181 may be omitted or more layers may be added. For example,the layer 120 may be omitted in cases where the hard mask layer 130 issufficiently durable to adequately transfer a modified pattern 109 tothe substrate 110.

Also, while “processing” through the various mask layers involvesetching an underlying layer, processing through the mask layers mayinvolve subjecting layers underlying the mask layers to anysemiconductor fabrication process. For example, processing may involveion implantation, diffusion doping, depositing, or wet etching, withoutlimitation, through the mask layers and onto underlying layers. Inaddition, the mask layers may be used as a stop or barrier for chemicalmechanical polishing (CMP) or CMP may be performed on any of the layersto allow for both planarization and etching of the underlying layers, asdisclosed in U.S. Provisional Patent Application No. 60/666,031, filedMar. 28, 2005, the entire disclosure of which is incorporated byreference herein.

It will be appreciated that the “substrate” to which patterns aretransferred may include a layer of a single material, a plurality oflayers of different materials, a layer or layers having regions ofdifferent materials or structures in them, etc. These materials mayinclude semiconductors, insulators, conductors, or combinations thereof.For example, the substrate may comprise doped polysilicon, an electricaldevice active area, a silicide, or a metal layer, such as a tungsten,aluminum or copper layer, or combinations thereof. In some embodiments,the mask features discussed herein may directly correspond to thedesired placement of conductive features, such as interconnects, in thesubstrate. In other embodiments, the substrate may be an insulator andthe location of mask features may correspond to the desired location ofinsulators, such as in damascene metallization. Examples of structuresformed in the substrate include gate stacks and shallow trench isolationstructures.

Further, in any of the acts described herein above, transferring apattern from an overlying level to an underlying level involves formingfeatures or spacers in the underlying level that generally correspond tofeatures or spacers in the overlying level. For example, the path oflines in the underlying level will generally follow the path of lines inthe overlying level and the location of other features in the underlyinglevel will correspond to the location of similar features or spacers inthe overlying level. The precise shapes and sizes of features andspacers may vary from the overlying level to the underlying level,however. For example, depending upon etch chemistries and conditions,the sizes of and relative spacing between the features and spacersforming the transferred patterns may be enlarged or diminished relativeto the pattern on the overlying level, while still resembling the sameinitial “pattern,” as are seen from the example of shrinking the linesin the embodiments described above. Thus, even with some changes in thedimensions of features or spacers, the transferred pattern, or patterns,is still considered to be the same pattern, or patterns, as the initialpattern. In contrast, forming spacers around mask features, e.g., thelines, may change the pattern.

CONCLUSION

Embodiments of the invention provide reverse pitch reduction flowenabling improved pattern transfer and the formation of differentlysized features in conjunction with the use of pitch multiplication.

In methods according to embodiments of the invention, a sequence oflayers of materials is formed that allow formation of a mask forprocessing a substrate to fabricate, for example, a memory chip or otherintegrated circuit device incorporating at least two regions on theactive surface thereof having structural elements of substantiallydiffering feature size. Thereafter, a first pattern of features isformed where conventional photolithography may be used to form the firstpattern defining features in the mask, the features being generallyformed in one region of the device, e.g., the peripheral region of thememory chip. Subsequently, a second pattern of spacers is formed usingpitch multiplication. The second pattern of spacers form an elementarray in another region of the device, e.g., the memory array of thememory chip, advantageously eliminating acts conventionally required toform the spacers when subsequent features of various sizes are requiredto be formed therewith. The quality of the pattern of spacers may beimproved and enhanced for subsequent transfer to the underlyingsubstrate while potentially eliminating additional layering, cleaning,and etching acts otherwise conventionally required in order to form adevice having respective features of diverse dimensions in the region ofthe memory array and in the peripheral region. The second pattern maycompletely or partially overlap the first pattern, or, in someembodiments, may be completely formed in different regions of thedevice, e.g., the periphery of the memory chip. The first pattern andthe second pattern may be selectively covered by a protective mask andsubjected to a so-called “loop chop” process to eliminate undesirableclosed loops in order to obtain a modified pattern for transfer to thesubstrate. Optionally, a “loop chop” may be omitted during fabricationfor a particular polarity of a level, thus saving an additional maskingstep.

Embodiments of the invention facilitate combining the patterns formingthe differently sized spacers and features and successfully transferringthe spacer and feature sizes and configurations to the underlyingsubstrate while subjecting the spacers, with their size below theminimum pitch of the photolithographic technique used for patterningthem, to fewer process acts which might compromise the quality of thetransfer.

In further embodiments of the invention, the pattern of pitch-multipliedresolution spacers may be configured as an array.

While particular embodiments of the invention have been shown anddescribed, numerous variations and other embodiments will occur to thoseof ordinary skill in the art. Accordingly, the invention is only limitedin terms of the scope of the appended claims.

1. A method for semiconductor device fabrication, comprising:photolithographically forming a first pattern of features over asubstrate, the features of the first pattern of features having a firstwidth; forming a second pattern of pitch-multiplied spacers having asecond width less than the first width subsequent tophotolithographically forming the first pattern of features; andconsolidating the first pattern of features and the second pattern ofpitch-multiplied spacers into a modified pattern of spacers andfeatures.
 2. The method of claim 1, wherein consolidating the firstpattern of features and the second pattern of pitch-multiplied spacersinto a modified pattern of spacers and features comprises forming aprotective mask over the first pattern of features and the secondpattern of pitch-multiplied spacers to selectively expose portions ofthe first pattern of features and the second pattern of pitch-multipliedspacers, etching the selectively exposed portions of the first patternof features and the second pattern of pitch-multiplied spacers to removethe exposed portions of the first pattern of features and the secondpattern of pitch-multiplied spacers.
 3. The method of claim 2, furthercomprising stripping the protective mask from the modified pattern ofspacers and features, and thereafter transferring the modified patternof spacers and features into the substrate.
 4. A semiconductor devicestructure, comprising: a semiconductor substrate; a pattern of featuresat a photolithographic resolution over the substrate in a first region,the features having a first width; a pattern of sub-photolithographicresolution spacers over the substrate in a second region, the pattern ofsub-photolithographic resolution spacers comprising a plurality ofspacers laterally adjacent and on opposite sides of a photoresist; thesub-lithographic spacers having a second width less than the firstwidth.
 5. The semiconductor device structure of claim 4, wherein thesecond region is a central array region and the first region is aperipheral region.
 6. The semiconductor device structure of claim 4,wherein the pattern of sub-photolithographic resolution spacers isconfigured as an array.
 7. The semiconductor device structure of claim4, further comprising a protective material around and over at least aportion of the pattern of features at a photolithographic resolution andthe pattern of sub-photolithographic resolution spacers.
 8. Thesemiconductor device structure of claim 7, wherein the pattern ofsub-photolithographic resolution spacers comprises a spacer having atleast two separate portions not covered by the protective material. 9.The semiconductor device structure of claim 4, wherein thesub-photolithographic resolution spacers comprise a material selectedfrom the group consisting of silicon, silicon oxides, and siliconnitrides.
 10. The method of claim 1, further comprising forming a maskover the substrate before photolithographically forming the firstpattern of features.
 11. The method of claim 10, wherein forming themask comprises depositing amorphous carbon, amorphous silicon, a silaneoxide, a nitride, or Al₂O₃.
 12. The method of claim 1, whereinphotolithographically forming a first pattern of features over asubstrate comprises exposing a photoresist overlying a hard mask toradiation through a reticle.
 13. The method of claim 12, whereinphotolithographically forming a first pattern of features over asubstrate further comprises anisotropically etching the hard mask. 14.The method of claim 1, wherein forming a second pattern ofpitch-multiplied spacers comprises forming a photoresist material overthe first pattern of features.
 15. The method of claim 14, furthercomprising exposing the photoresist material to radiation through areticle to form lines of the photoresist material separated by trenches.16. The method of claim 15, further comprising etching the photoresistmaterial to increase a width of the trenches and decrease a width of thelines of the photoresist material.
 17. The method of claim 16, furthercomprising conformally depositing a spacer material over the firstpattern of features and the second pattern of pitch-multiplied spacers.18. The method of claim 17, further comprising anisotropically etchingthe spacer material to form spacers of the second pattern ofpitch-multiplied spacers.
 19. The method of claim 18, further comprisingremoving at least a portion of the photoresist material between adjacentspacers of the second pattern of pitch-multiplied spacers.
 20. A methodfor semiconductor device fabrication, comprising: forming a hard maskover a substrate; photolithographically forming a first pattern offeatures over the hard mask, the features of the first pattern offeatures having a first width; forming a second pattern ofpitch-multiplied spacers having a second width less than the first widthover the hard mask after photolithographically forming the first patternof features; and removing a portion of the hard mask to transfer thefirst pattern of features and the second pattern of pitch-multipliedspacers into a modified pattern of spacers and features in the hardmask.